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1997 data sheet description the m pd78056fy,78058fy reduce the electromagnetic interference (emi) noise in comparison with the conven- tional m pd78056y,78058y. the m pd78056fy,78058fy belong to the m pd78058fy subseries products of the 78k/ 0 series. these microcontrollers include a variety of peripheral hardware, such as an 8-bit resolution a/d converter, 8-bit resolution d/a converter, timer, serial interface (supports i 2 c bus mode), real-time output ports, and interrupt functions. the m pd78p058fy, a one-time prom which can be operated in the same supply voltage range as for the mask rom version, and various development tools are also available. detailed function descriptions are provided in the following users manual. be sure to read them before designing. m pd78058f, 78058fy subseries user's manual: u12068e 78k/0 series users manual-instruction: u12326e features ? emi noise reduction version (the overall peak level is reduced by 5 to 10 db.) ? large on-chip rom & ram note this package is available only for the m pd78058fy. ? external memory expansion space: 64 kbytes ? minimum instruction execution time can be varied from high-speed (0.4 m s) to ultra-low-speed (122 m s) ? i/o ports: 69 (n-ch open-drain: 4) ? 8-bit resolution a/d converter: 8 channels ? 8-bit resolution d/a converter: 2 channels ? serial interface: 3 channels (supports i 2 c bus mode: 1 channel) ? timer: 5 channels ? supply voltage: v dd = 2.7 to 6.0 v applications cellular phones, pagers, printers, av equipment, air conditioners, cameras, ppc, fuzzy home appliances, vending machines, etc. the mark shows major revised points . mos integrated circuit 8-bit single-chip microcontroller m pd78056fy,78058fy the information in this document is subject to change without notice. document no. u12142ej2v0ds00 (2nd edition) date published october 1997 n printed in japan products items internal high- speed ram m pd78056fy m pd78058fy 48 kbytes 60 kbytes 1024 bytes program memory (rom) buffer ram internal expansion ram 80-pin plastic qfp (14 14 mm, resin thickness 2.7 mm) 80-pin plastic qfp (14 14 mm, resin thickness 1.4 mm) 80-pin plastic tqfp (fine pitch) (12 12 mm) note data memory packages none 1024 bytes 32 bytes
2 m pd78056fy, 78058fy ordering information part number package m pd78056fygc- -3b9 80-pin plastic qfp (14 14 mm, resin thickness 2.7 mm) m pd78056fygc- -8bt 80-pin plastic qfp (14 14 mm, resin thickness 1.4 mm) m pd78058fygc- -3b9 80-pin plastic qfp (14 14 mm, resin thickness 2.7 mm) m pd78058fygc- -8bt 80-pin plastic qfp (14 14 mm, resin thickness 1.4 mm) m pd78058fygk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) caution the m pd78056fygc, m pd78058fygc come in two types of packages (see 12 package drawings). for the packages that can be supplied, consult your local nec sales representative. remark denotes the rom code number.
3 m pd78056fy, 78058fy 78k/0 series product development these products are a further development in the 78k/0 series. the designations appearing inside the boxes are subseries names. note under planning pd78058f pd78054 pd78018f pd78014 pd780001 pd78002 pd78083 pd78058fy pd78054y pd78018fy pd78014y pd78002y 100-pin 100-pin 100-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 42/44pin control products in mass production products under development y subseries products are compatible with i 2 c bus. a timer was added to the pd78054 and external interface function was enhanced emi noise reduction version of the pd78078 rom-less versions of the pd78078 emi noise reduction version of the pd78054 emi noise reduction version of the pd78018f uart and d/a converter were added to the pd78014 and i/o was enhanced a/d converter of the pd780024 was enhanced low-voltage (1.8 v) operation versions of the pd78014 with several rom and ram capacities are available an a/d converter and 16-bit timer were added to the pd78002 an a/d converter was added to the pd78002 basic subseries for control on-chip uart, capable of operating at a low voltage (1.8 v) pd780018ay 100-pin serial i/o of the pd78078y was enhanced and only selected functions are provided serial i/o of the pd78054 was enhanced, emi noise reduction version serial i/o of the pd78018f was enhanced, emi noise reduction version pd78078 pd78070a pd78078y pd78070ay m pd78075b m m pd78075by m mm m mm pd780058 pd780058y note 80-pin mm mm mm mm m pd780034 pd780024 pd78014h pd780034y pd780024y 64-pin 64-pin 64-pin mm mm m mm m m m m m m m m m m m m m fip tm drive pd780208 pd78044h pd78044f 100-pin 80-pin 80-pin m pd780228 100-pin m m m the i/o and fip c/d of the pd78044f were enhanced, display output total: 53 the i/o and fip c/d of the pd78044h were enhanced, display output total: 48 n-ch open drain i/o was added to the pd78044h, display output total: 34 basic subseries for driving fip, display output total: 34 m m m inverter control pd780308 pd78064b pd78064 100-pin 100-pin 100-pin m m sio of the pd78064 was enhanced and rom and ram were expanded emi noise reduction version of the pd78064 subseries for driving lcds, on-chip uart m pd780308y m pd78064y m lcd drive m m iebus tm supported m lv pd78p0914 64-pin m on-chip pwm output, lv digital code decoder, hsync counter 78k/0 series a/d converter of the pd780924 was enhanced on-chip inverter control circuit and uart, emi noise reduction version m pd780964 pd780924 64-pin 64-pin m m inverter control, timer and sio of the pd780964 were enhanced and rom and ram were expanded pd780988 64-pin m pd78098b 80-pin m emi noise reduction version of the m pd78098 pd78098 80-pin m the iebus contorller was added to the m pd78098 meter control pd780973 80-pin m on-chip the controller /driver for automobile meter drive m
4 m pd78056fy, 78058fy the major functional differences among the y subseries are shown below. function rom capacity serial interface i/o v dd min. subseries value control m pd78075by 32 k to 40 k 3-wire/2-wire/i 2 c : 1 ch 88 1.8 v m pd78078y 48 k to 60 k 3-wire with automatic send/receive function : 1 ch m pd78070ay 3-wire/uart : 1 ch 61 2.7 v m pd780018ay 48 k to 60 k 3-wire with automatic send/receive function : 1 ch 88 time division 3-wire : 1 ch i 2 c bus (supports multimaster) : 1 ch m pd780058y 24 k to 60 k 3-wire/2-wire/i 2 c : 1 ch 68 1.8 v 3-wire with automatic send/receive function : 1 ch 3-wire/time division uart : 1 ch m pd78058fy 48 k to 60 k 3-wire/2-wire/i 2 c : 1 ch 69 2.7 v m pd78054y 16 k to 60 k 3-wire with automatic send/receive function : 1 ch 2.0 v 3-wire/uart : 1 ch m pd780034y 8 k to 32 k uart : 1 ch 51 1.8 v m pd780024y 3-wire : 1 ch i 2 c bus (supports multimaster) : 1 ch m pd78018fy 8 k to 60 k 3-wire/2-wire/i 2 c : 1 ch 53 3-wire with automatic send/receive function : 1 ch m pd78014y 8 k to 32 k 3-wire/2-wire/sbi/i 2 c : 1 ch 2.7 v 3-wire with automatic send/receive function : 1 ch m pd78002y 8 k to 16 k 3-wire/2-wire/sbi/i 2 c : 1 ch lcd m pd780308y 48 k to 60 k 3-wire/2-wire/i 2 c : 1 ch 57 2.0 v driving 3-wire/time-division uart : 1 ch 3-wire : 1 ch m pd78064y 16 k to 32 k 3-wire/2-wire/i 2 c : 1 ch 3-wire/uart : 1 ch remark the functions, except for the serial interface, are the same as those of subseries without y.
5 m pd78056fy, 78058fy 48 kbytes 60 kbytes 1024 bytes 32 bytes none 1024 kbytes 64 kbytes 8 bits 32 registers (8 bits 8 registers 4 banks) on-chip instruction execution time cycle modification function 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (at 5.0-mhz operation) 122 m s (at 32.768-khz operation) ? 16-bit operation ? multiplication/division (8 bits 8 bits,16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd correction, etc. total : 69 ? cmos input : 0 2 ? cmos i/o : 63 ? n-ch open-drain i/o : 0 4 ? 8-bit resolution 8 channels ? 8-bit resolution 2 channels ? 3-wire serial i/o/2-wire serial i/o/i 2 c bus mode selectable: 1 channel ? 3-wire serial i/o mode (on-chip max. 32 bytes automatic data transmit/receive function): 1 channel ? 3-wire serial i/o/uart mode selectable: 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (14-bit pwm output 1) 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (at main system clock 5.0-mhz operation) 32.768 khz (at subsystem clock 32.768-khz operation) 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (at main system clock 5.0-mhz operation) internal : 13, external : 7 internal : 1 1 overview of function product name item m pd78056fy m pd78058fy serial interface memory space general registers minimum instruction execution time instruction set i/o ports a/d converter d/a converter timer timer output clock output buzzer output internal memory rom high-speed ram buffer ram expanded ram vectored- interrupt source test input supply voltage operating ambient temperature package internal : 1, external : 1 v dd = 2.7 to 6.0 v t a = C 40 to + 85 c ? 80-pin plastic qfp (14 14 mm, resin thickness 2.7 mm) ? 80-pin plastic qfp (14 14 mm, resin thickness 1.4 mm) ? 80-pin plastic tqfp (fine pitch) (12 12 mm) note note m pd78058fy only when main system clock selected when subsystem clock selected maskable non-maskable software
6 m pd78056fy, 78058fy contents 1. pin configuration (top view) .............................................................................................. 7 2. block diagram ......................................................................................................................... 9 3 pin functions .......................................................................................................................... 10 3.1 port pins ............................................................................................................................... 10 3.2 non-port pins ........................................................................................................................ 12 3.3 pin i/o circuits and recommended connection of unused pins ................................. 14 4. memory space ............................................................................................................................ 18 5. peripheral hardware function features .................................................................. 19 5.1 ports ............................................................................................................................... ........ 19 5.2 clock generator .................................................................................................................... 20 5.3 timer/event counter ............................................................................................................ 20 5.4 clock output control circuit .............................................................................................. 23 5.5 buzzer output control circuit ............................................................................................ 23 5.6 a/d converter ........................................................................................................................ 24 5.7 d/a converter ........................................................................................................................ 25 5.8 serial interfaces .................................................................................................................... 25 5.9 real-time output port functions ....................................................................................... 27 6. interrupt functions and test functions .................................................................... 28 6.1 interrupt functions ............................................................................................................. 28 6.2 test functions ...................................................................................................................... 32 7. external device expansion functions .......................................................................... 33 8. standby function .................................................................................................................... 33 9. reset function .......................................................................................................................... 33 10. instruction set ......................................................................................................................... 34 11. electrical specifications ................................................................................................... 37 12. package drawings .................................................................................................................. 63 13. recommended soldering conditions ............................................................................. 66 appendix a. development tools ........................................................................................... 68 appendix b. related documents .......................................................................................... 70
7 m pd78056fy, 78058fy 1. pin configuration (top view) ? 80-pin plastic qfp (14 14, resin thickness 2.7 mm) ? 80-pin plastic tqfp (fine pich) (12 12 mm) m pd78056fygc- -3b9 m pd78058fygk- -be9 m pd78058fygc- -3b9 ? 80-pin plastic qfp (14 14, resin thickness 1.4 mm) m pd78056fygc- -8bt m pd78058fygc- -8bt cautions 1. connect directly the internally connected (ic) pin to v ss . 2. the av dd pin functions as both an a/d converter power supply and a port power supply. when the m pd78056fy and 78058fy are used in applications where the noise generated inside the microcontroller needs to be reduced, connect the av dd pin to another power supply which has the same potential as v dd . 3. the av ss pin functions as both an a/d and d/a converter ground and as a port ground. when the m pd78056fy and 78058fy are used in applications where the noise generated inside the microcontroller needs to be reduced, connect the av ss pin to a ground line other than v ss . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p15/ani5 p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/rxd p71/so2/txd p72/sck2/asck p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0/sda0 p26/so0/sb1/sda1 p27/sck0/scl p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss p56/a14 p57/a15 p60 p61 p62 p63 p64/rd 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 reset p127/rtp7 p126/rtp6 p125/rtp5 p124/rtp4 p123/rtp3 p122/rtp2 p121/rtp1 p120/rtp0 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p67/astb p66/wait p65/wr 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref0 av dd xt1/p07 xt2 ic x1 x2 v dd p06/intp6 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1/ti01 p00/intp0/ti00
8 m pd78056fy, 78058fy pcl : programmable clock rd : read strobe reset : reset rtp0 to rtp7 : real-time output port rxd : receive data sb0, sb1 : serial bus sck0 to sck2 : serial clock scl : serial clock sda0, sda1 : serial data si0 to si2 : serial input so0 to so2 : serial output stb : strobe ti00, ti01 : timer input ti1, ti2, : timer input to0 to to2 : timer output txd : transmit data v dd : power supply v ss : ground wait : wait wr : write strobe x1, x2 : crystal (main system clock) xt1, xt2 : crystal (subsystem clock) a8 to a15 : address bus ad0 to ad7 : address/data bus ani0 to ani7 : analog input ano0, ano1 : analog output asck : asynchronous serial clock astb : address strobe av dd : analog power supply av ref0 , av ref1 : analog reference voltage av ss : analog ground busy : busy buz : buzzer clock ic : internally connected intp0 to intp6 : interrupt from peripherals p00 to p07 : port0 p10 to p17 : port1 p20 to p27 : port2 p30 to p37 : port3 p40 to p47 : port4 p50 to p57 : port5 p60 to p67 : port6 p70 to p72 : port7 p120 to p127 : port12 p130, p131 : port13
9 m pd78056fy, 78058fy 2. block diagram remark the internal rom and ram capacity depends on the product. to0/p30 ti00/intp0/p00 ti01/intp1/p01 16-bit timer/ event counter to1/p31 ti1/p33 8-bit timer/ event counter 1 to2/p32 ti2/p34 8-bit timer/ event counter 2 watchdog timer watch timer serial interface 0 si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 serial interface 1 si2/rxd/p70 so2/txd/p71 sck2/asck/p72 ani0/p10 to ani7/p17 av ref0 ano0/p130, ano1/p131 av ref1 intp0/p00 to intp6/p06 buz/p36 pcl/p35 serial interface 2 a/d converter d/a converter interrupt control buzzer output clock output control port0 port1 port2 port3 port4 port5 port6 port7 port12 port13 real-time output port external access system control v dd v ss av dd av ss ic 78k/0 cpu core rom ram p00 p01 to p06 t07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p72 p120 to p127 p130, p131 rtp0/p120 to rtp7/p127 ad0/p40 to ad7/p47 a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 xt1/p07 xt2
10 m pd78056fy, 78058fy 3. pin functions 3.1 port pins (1/2) alternate function pin name i/o input only input input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. input/ output input only port 1 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. note 2 input/ output input/ output port 2 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. port 3 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. input/ output input/ output port 4 8-bit input/output port. input/output can be specified in 8-bit unit. when used as an input port, on-chip pull-up resistor can be used by software. test input flag (krif) is set to 1 by falling edge detection. intp0/ti00 intp1/ti01 intp2 intp3 intp4 intp5 intp6 xt1 ani0 to ani7 si1 so1 sck1 stb busy si0/sb0/sda0 so0/sb1/sda1 sck0/scl to0 to1 to2 ti1 ti2 pcl buz ad0 to ad7 p00 p01 p02 p03 p04 p05 p06 p07 note 1 p10 to p17 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p34 p35 p36 p37 p40 to p47 input function port 0 8-bit i/o port input input after reset input input input input input notes 1. when using the p07/xt1 pins as an input port, set 1 in bit 6 (frc) of the processor clock control register. on-chip feedback resistor of the subsystem clock oscillator should not be used. 2. when using the p10/ani0 to p17/ani7 pins as the a/d converter analog input pins, use of the on-chip pull- up resistor is cancelled automatically.
11 m pd78056fy, 78058fy 3.1 port pins (2/2) alternate function function pin name i/o input/ output input/ output p50 to p57 when used as an input port, on-chip pull-up resistor can be used by software. p60 p61 p62 p63 p64 p65 p66 p67 p70 p71 p72 p120 to p127 p130, p131 input/ output input/ output input/ output n-ch open-drain input/output port. on-chip pull-up resistor can be specified by mask option. led can be driven directly. after reset port 5 8-bit input/output port. led can be driven directly. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. port 6 8-bit input/outport port. input/output can be specified bit-wise. port 13 2-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. port 12 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. port 7 3-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used by software. input input input input input input a8 to a15 rd wr wait astb si2/rxd so2/txd sck2/asck rtp0 to rtp7 ano0, ano1 caution for pins which also function as port pins, do not perform the following operations during a/d conversion. if these operations are performed, the total error ratings cannot be kept (except for lcd segment output alternate-function pin). (1) rewrite the output latch which the pin is used as a port pin. (2) change the output level of the pin used as an output pin, even if it is not used as a port pin.
12 m pd78056fy, 78058fy alternate function function pin name i/o input external interrupt request input by which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be specified. input serial interface serial data input. output serial interface serial data output. serial interface serial data input/output. input /output input /output serial interface serial clock input/ output serial interface automatic transmit/receive strobe output. serial interface automatic transmit/receive busy input. output input input output output input input output asynchronous serial interface serial data input. asynchronous serial interface serial data output. 3.2 non-port pins (1/2) p00/ti00 p01/ti01 p02 p03 p04 p05 p06 p25/sb0/sda0 p20 p70/rxd p26/sb1/sda1 p21 p71/txd p25/si0/sda0 p26/so0/sda1 p25/si0/sb0 p26/so0/sbi p27/scl p22 p72/asck p27/sck0 p23 p24 p70/si2 p71/so2 p72/sck2 p00/intp0 p01/intp1 p33 p34 p30 p31 p32 p35 p36 p120 to p127 p40 to p47 output intp0 intp1 intp2 intp3 intp4 intp5 intp6 si0 si1 si2 so0 so1 so2 sb0 sb1 sda0 sda1 sck0 sck1 sck2 scl stb busy rxd txd asck ti00 ti01 ti1 ti2 to0 to1 to2 pcl buz rtp0 to rtp7 ad0 to ad7 output clock output (for main system clock, subsystem clock trimming). buzzer output. real-time output port by which data is output in synchronization with a trigger. low-order address/data bus at external memory expansion. input /output after reset input input input input input input input input input input input input input input input input external count clock input to the 16-bit timer (tm0) asynchronous serial interface serial clock input. capture trigger signal input to the capture register (cr00) external count clock input to the 8-bit timer (tm1) external count clock input to the 8-bit timer (tm2) 16-bit timer (tm0) output (alternate function as 14-bit pwm output) 8-bit timer (tm1) output 8-bit timer (tm2)
13 m pd78056fy, 78058fy p66 p67 p10 to p17 p130, p131 p07 3.2 non-port pins (2/2) alternate function function pin name i/o input output input output input input input input input wait astb ani0 to ani7 ano0, ano1 av ref0 av ref1 av dd av ss reset x1 x2 xt1 xt2 v dd v ss ic wait insertion at external memory access. strobe output which latches the address information output at port 4 to access external memory. a/d converter analog input. d/a converter analog output. a/d converter reference voltage input. d/a converter reference voltage input. a/d converter analog power supply (shared with the port power supply) a/d and d/a converter ground potential (shared with the port ground potential) system reset input. main system clock oscillation crystal connection. subsystem clock oscillation crystal connection. positive power supply (except for port). ground potential (except for port). internally connected. connect directly to v ss . after reset input input input input input cautions 1. the av dd pin functions as both an a/d converter power supply and a port power supply. when the m pd78056fy and 78058fy are used in applications where the noise generated inside the microcontroller needs to be reduced, connect the av dd pin to another power supply which has the same potential as v dd . 2. the av ss pin functions as both an a/d converter and d/a converter ground and as a port ground. when the m pd78056fy and 78058fy are used in applications where the noise generated inside the microcontroller needs to be reduced, connect the av ss pin to a ground line other than v ss . a8 to a15 rd wr output output high-order address bus at external memory expansion. external memory read operation strobe signal output. external memory write operation strobe signal output. input input p50 to p57 p64 p65
14 m pd78056fy, 78058fy 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, see figure 3-1. table 3-1. input/output circuit type of each pin (1/2) input/output circuit type 2 8-d 16 11-c 8-d 5-j 8-d 5-j 8-d 10-c 5-j 8-d 5-j 5-o 5-j 13-i 5-j input input/output input input/output connected to v ss . independently connect to v ss through resistor. connect to v dd . p00/intp0/ti00 p01/intp1/ti01 p02/intp2 p03/intp3 p04/intp4 p05/intp5 p06/intp6 p07/xt1 p10/ani0 to p17/ani7 p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0/sda0 p26/so0/sb1/sda1 p27/sck0/scl p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p37 p40/ad0 to p47/ad7 p50/a8 to p57/a15 p60 to p63 p64/rd p65/wr p66/wait p67/astb pin name i/o recommended connection when not used independently connect to v dd or v ss through resistor. independently connect to v dd through resistor. independently connect to v dd or v ss through resistor. independently connect to v dd through resistor. independently connect to v dd or v ss through resistor.
15 m pd78056fy, 78058fy table 3-1. input/output circuit type of each pin (2/2) input/output circuit type p70/si2/rxd p71/so2/txd p72/sck2/asck p120/rtp0 to p127/rtp7 p130/ano0 , p131/ano1 reset xt2 av ref0 av ref1 pin name i/o recommended connection when not used 8-d 5-j 8-d 5-j 12-b 2 16 input/ output input/ output input av dd av ss independently connect to v dd or v ss through resistor. independently connect to v ss through resistor. leave open. connect to v ss . connect to v dd . connect to another power supply which has the same potential as v dd . connect to another ground line which has the same potential as v ss . connect directly to v ss . ic
16 m pd78056fy, 78058fy figure 3-1. pin input/output circuits (1/2) type 2 in type 8-d pullup enable data output disable av p-ch n-ch p-ch in/out dd av dd type 10-c enable type 11-c pullup enable data output disable av p-ch n-ch p-ch in/out ss av dd type 5-j input enable type 5-o pullup enable data output disable av p-ch n-ch p-ch in/out dd av dd schmitt-triggered input with hysteresis characteristic pullup enable data output disable in/out v ref input dd (threshold voltage) av p-ch n-ch p-ch dd av p-ch + - comparator pullup enable data output disable av p-ch n-ch p-ch in/out dd av dd open drain av ss av dd av ss av ss av ss n-ch ss av
17 m pd78056fy, 78058fy figure 3-1. pin input/output circuits (2/2) type 12-b type 16 pullup enable data output disable av p-ch n-ch p-ch in/out dd av dd n-ch input enable type 13-i data output disable n-ch p-ch in/out av dd av dd rd mask option middle-high voltage input buffer p-ch analog output voltage xt1 feed back cut-off xt2 p-ch av ss av ss av ss
18 m pd78056fy, 78058fy 4. memory space figure 4-1 shows the memory map of the m pd78056fy,78058fy. figure 4-1. memory map notes 1. m pd78058fy only 2. when the external device expansion function is used with the m pd78058fy, set the internal rom capacity to 56 kbytes or less using the memory size switching register (ims). 3. the internal rom capacity and internal high-speed ram capacity depend on the products (see the table below). internal rom last address nnnnh target product bfffh m pd78056fy m pd78058fy efffh special function registers (sfr) 256 8 bits general registers 32 8 bits internal high-speed ram use prohibited buffer ram 32 8 bits use prohibited external memory internal rom note 3 data memory space program memory space ffffh ff00h feffh fee0h fedfh fb00h faffh fae0h fadfh fac0h fabfh fa80h fa7fh nnnnh + 1 nnnnh 0000h use prohibited internal expanded ram 1024 8 bits use prohibited note 2 fa7fh f800h f7ffh f400h f3ffh f000h program area callf entry area program area callt table area vector table area nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h note 1024 8 bits
19 m pd78056fy, 78058fy 5. peripheral hardware function features 5.1 ports the following 3 types of i/o ports are available. ? cmos input (p00, p07) : 2 ? cmos input/output (p01 to p06, port 1 to port 5, p64 to p67, port 7, port 12, port 13) : 63 ? n-channel open-drain input/output (p60 to p63) : 4 total : 69 table 5-1. port functions pin name function dedicated input port pins input/output port pins. input/output specifiable bit-wise. when used as input/output port pins, on-chip pull-up resistor can be used by software. input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. input/output port pins. input/output specifiable in 8-bit units. when used as input port pins, on-chip pull-up resistor can be used by software. test input flag (krif) is set to 1 by falling edge detection. input/output port pins. input/output specifiable bit-wise. when used as input port pins, on-chip pull-up resistor can be used by software. led direct drive capability. n-channel open-drain input/output port pins. input/output specifiable bit-wise. on-chip pull-up resistor can be used by mask option. led direct drive capability. input/output port pins. input/output specifiable bit-wise. when used as input/output port pins, on-chip pull-up resistor can be used by software. input/output port pins. input/output specifiable bit-wise. when used as input/output port pins, on-chip pull-up resistor can be used by software. input/output port pins. input/output specifiable bit-wise. when used as input/output port pins, on-chip pull-up resistor can be used by software. input/output port pins. input/output specifiable bit-wise. when used as input/output port pins, on-chip pull-up resistor can be used by software. name port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 12 port 13 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p63 p64 to p67 p70 to p72 p120 to p127 p130, p131 p00, p07 p01 to p06
20 m pd78056fy, 78058fy 5.2 clock generator two types of generators, a main system clock generator and a subsystem clock generator, are avaibable. the minimum instruction execution time can also be changed. ? 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (main system clock: at 5.0-mhz operation) ? 122 m s (subsystem clock: at 32.768-khz operation) figure 5-1. clock generator block diagram 16-bit timer/event counter 8-bit timer/event counter watch timer watchdog timer external event counter 2 channels operation mode timer output pwm output square wave output 1 output 1 output 2 input pulse width measurement 2 outputs interrupt request 2 1 1 2 function 1 channel 1 channel 2 channels 1 channel interval timer 1 channel 1 output 2 outputs one-shot pulse output 1 output test input 1 input 5.3 timer/event counter 5 timer/event counter channels are incorporated. ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel table 5-2. operation of timer/event counter xt1/p07 xt2 x1 x2 f xt f xx subsystem clock oscillator watch timer, clock output function prescaler main system clock oscillator clock to peripheral hardware cpu clock (f cpu ) standby control circuit wait control circuit to intp0 sampling clock 2 f xx 2 2 f xx 2 3 f xx 2 4 f xx f xt 2 prescaler selector selector f x f x 2 stop divider 2 1
21 m pd78056fy, 78058fy figure 5-2. 16-bit timer/event counter block diagram figure 5-3. 8-bit timer/event counter block diagram internal bus selector selector 16-bit timer register (tm0) clear output control circuit pwm pulse output control circuit 16-bit capture/ compare register internal bus intp1 inttm00 to0/p30 inttm01 intp0 ti01/p01/intp1 watch timer output 2f xx f xx f xx /2 2 f xx /2 ti00/p00/intp0 16-bit capture/ compare register (cr01) (cr00) edge detction circuit match match selector internal bus 8-bit compare register (cr10) 8-bit timer register 1 (tm1) clear match selector output control circuit output control circuit inttm1 to2/p32 inttm2 to1/p31 clear match selector selector selector selector 8-bit compare register (cr20) 8-bit timer register 2 (tm2) internal bus f xx /2-f xx /2 f xx /2 9 11 ti1/p33 f xx /2-f xx /2 f xx /2 9 11 ti2/p34
22 m pd78056fy, 78058fy figure 5-4. watch timer block diagram figure 5-5. watchdog timer block diagram inttm3 intwt 5-bit counter prescaler selector selector selector selector f xx /2 f xt 7 f w 2 f w 4 2 f w 5 2 f w 6 2 f w 7 2 f w 8 2 f w 9 2 f w 14 2 f w 13 to 16-bit timer/ event counter control circuit 8-bit counter prescaler intwdt non-maskable interrupt request intwdt maskable interrupt request reset selector 2 f xx 4 2 f xx 5 2 f xx 6 2 f xx 7 2 f xx 8 2 f xx 9 2 f xx 11 2 f xx 3
23 m pd78056fy, 78058fy 5.4 clock output control circuit clock with the following frequencies can be output as clock output. ? 19.5 khz/39.1 khz/78.1 khz/156 khz/313 khz/625 khz/1.25 mhz/2.5 mhz/5.0 mhz (main system clock: at 5.0-mhz operation) ? 32.768 khz (subsystem clock: at 32.768-khz operation) figure 5-6. clock output control block diagram 5.5 buzzer output control circuit clock with the following frequencies can be output as buzzer output. ? 1.2 khz/2.4 khz/4.9 khz/9.8 khz (main system clock: at 5.0-mhz operation) figure 5-7. buzzer output control circuit block diagram selector synchronization circuit output control circuit pcl/p35 f xx f xx f xx f xx f xx f xx /2 /2 2 /2 3 /2 4 /2 5 f xx /2 6 f xx f xt /2 7 selector output control circuit buz/p36 f xx /2 9 f xx /2 10 f xx /2 11
24 m pd78056fy, 78058fy 5.6 a/d converter an a/d converter of 8-bit resolution 8 channels is incorporated. the following two types of a/d conversion operation start-up methods are available. ? hardware start ? software start figure 5-8. a/d converter block diagram tap selector intad av dd intp3 internal bus av ref0 av ss a/d conversion result register (adcr) control circuit successive approximation register (sar) edge detection circuit ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 intp3/p03 selector sample & hold circuit voltage comparator series resistor string av ss
25 m pd78056fy, 78058fy n = 0, 1 m = 4, 5 x = 1, 2 5.8 serial interfaces 3 channels of the clocked serial interface are incorporated. ? serial interface channel 0 ? serial interface channel 1 ? serial interface channel 2 table 5-3. types and functions of serial interface 5.7 d/a converter a d/a converter of 8-bit resolution 2 channels is available. the conversion method is the r-2r resistor ladder method. figure 5-9. d/a converter block diagram function 3-wire serial i/o mode with auto- matic transmission/reception function 2-wire serial i/o mode i 2 c bus mode asynchronous serial interface (uart) mode 3-wire serial i/o mode (msb/lsb first switchable) (msb/lsb first switchable) (msb first) (msb first) (dedicated baud rate generator incorporated) serial interface channel 0 serial interface channel 1 serial interface channel 2 (msb/lsb first switchable) (msb/lsb first switchable) internal bus selector d/a conversion value set register n (dacsn) av ref1 av ss damm inttm x dacsn write anon d/a converter mode register
26 m pd78056fy, 78058fy figure 5-10. serial interface channel 0 block diagram figure 5-11. serial interface channel 1 block diagram acknowledge output circuit output latch serial i/o shift register 0 (sio0) internal bus interrupt request signal generator serial clock counter stop condition/start condition acknowledge detection circuit serial clock control circuit selector selector selector si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 intcsi0 to2 f xx /2-f xx /2 8 internal bus interrupt request signal generator handshake control circuit buffer ram serial clock control circuit selector serial clock counter serial i/o shift register 1 (sio1) automatic data transmit/ receive address pointer (adtp) automatic data transmit/receive interval specification register (adti) 5-bit counter intcsi1 f xx /2-f xx /2 to2 8 si1/p20 so1/p21 stb/p23 busy/p24 sck1/p22 match
27 m pd78056fy, 78058fy figure 5-12. serial interface channel 2 block diagram 5.9 real-time output port functions data set previously in the real-time output buffer register is transferred to the output latch by hardware concurrently with timer interrupt request and external interrupt request generation in order to output to off-chip. this is a real-time output function. pins to output to off-chip are called real-time output ports. by using a real-time output port, a signal which has no jitter can be output. this is most applicable to control of stepping motors, etc. figure 5-13. real-time output port block diagram rxd/si2/p70 txd/so2/p71 asck/sck2/p72 intser intsr/intcsi2 intst f xx -f xx /2 10 internal bus receive buffer register (rxb/sio2) direction control circuit receive shift register (rxs) receive control circuit direction control circuit transmit shift register (txs/sio2) transmit control circuit sck output control circuit baud rate generator internal bus p127 p120 output latch real-time output buffer register higher 4 bits (rtbh) real-time output buffer register higher 4 bits (rtbl) real-time output port mode register (rtpm) output trigger control circuit intp2 inttm1 inttm2
28 m pd78056fy, 78058fy ? non-maskable : 1 ? maskable : 20 ? software : 1 interrupt type note 1 default priority name watchdog timer overflow (watchdog timer mode 1 selected) interrupt source trigger watchdog timer overflow (interval timer mode selected) 1 2 3 4 5 6 7 intp0 intp1 intp2 intp3 intp4 intp5 intp6 0006h 0008h 000ah 000ch 000eh 0010h 0012h (c) end of serial interface channel 0 transfer internal/ external vector table address basic configuration type note 2 CCC intwdt non-maskable (a) internal 0004h 0 intwdt (b) pin input edge detection external maskable intcsi0 8 0014h (b) (d) 6. interrupt functions and test functions 6.1 interrupt functions there are 22 interrupt functions of 3 different kinds, as shown below. internal intcsi1 0016h 9 intser 10 0018h intst 12 end of serial interface channel 1 transfer table 6-1. interrupt source list (1/2) generation of serial interface channel 2 uart receive error 11 intsr 001ah end of serial interface channel 2 uart reception end of serial interface channel 2 3-wire transfer intcsi2 end of serial interface channel 2 uart transmission 001ch notes 1. the default priority is a priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest order and 18, the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1, respectively.
29 m pd78056fy, 78058fy table 6-1. interrupt source list (2/2) name interrupt source reference time interval signal from watch timer generation of match signal of 16-bit timer register and capture/compare register (cr00) generation of match signal of 16-bit timer register and capture/compare register (cr01) generation of match signal of 8-bit timer/event counter 1 generation of match signal of 8-bit timer/ event counter 2 end of conversion by a/d converter brk instruction execution intad brk notes 1. the default priority is a priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest order and 18, the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1, respectively. interrupt type software 13 inttm3 001eh (b) internal/ external vector table address basic configuration type note 2 trigger 14 inttm00 0020h internal inttm01 15 0022h inttm1 16 0024h inttm2 17 note 1 default priority maskable 18 0028h 003eh (e) 0026h
30 m pd78056fy, 78058fy figure 6-1. interrupt function basic configuration (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0) internal bus priority control circuit vector table address generator standby release si g nal interrupt request mk internal bus ie pr isp if priority control circuit vector table address generator standby release signal interrupt request mk ie pr isp if priority control circuit vector table address generator sampling clock select register (scs) external interrupt mode register (intm0) edge detection circuit sampling clock internal bus standby release si g nal interrupt request
31 m pd78056fy, 78058fy figure 6-1. interrupt function basic configuration (2/2) (d) external maskable interrupt (except intp0) (e) software interrupt if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specification flag mk ie pr isp if priority control circuit vector table address generator external interrupt mode register (intm0, intm1) edge detection circuit internal bus standby release si g nal interrupt request priority control circuit vector table address generator internal bus interrupt request
32 m pd78056fy, 78058fy 6.2 test functions there are two test functions as shown in table 6-2. table 6-2. test input source list internal/external name intpt4 intwt watch timer overflow port 4 falling edge detection internal external test input source trigger figure 6-2. test function basic configuration if : test input flag mk : test mask flag mk internal bus if standby release signal test input
33 m pd78056fy, 78058fy 7. external device expansion functions the external device expansion functions connect external devices to areas other than the internal rom, ram and sfr. ports 4 to 6 are used for external device connection. 8. standby function there are the following two standby functions to reduce the system power consumption. ? halt mode : the cpu operating clock is stopped. the average consumption current can be reduced by intermittent operation in combination with the normal operating mode. ? stop mode : the main system clock oscillation is stopped. the whole operation by the main system clock is stopped, so that the system operates with ultra-low power consumption using only the subsystem clock. figure 8-1. stand-by function note the power consumption can be reduced by stopping the main system clock. when the cpu is operating on the subsystem clock, set bit 7 (mcc) in the processor clock control register (pcc) to stop the main system clock. the stop instruction cannot be used. 9. reset function there are the following two reset methods. ? external reset input by reset pin ? internal reset by watchdog time runaway time detection caution when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. remark css : bit 4 in the pcc main system clock operation stop mode (main system clock oscillation stopped) halt mode (clock supply to cpu is stopped, oscillation) subsystem clock operation note halt mode note (clock supply to cpu is stopped, oscillation) interrupt request interrupt request interrupt request halt instruction halt instruction stop instruction css = 1 css = 0
34 m pd78056fy, 78058fy 10. instruction set (1) 8-bit instructions mov, xch, add addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz note except r = a second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a r add addc sub subc and or xor cmp mov mov mov mov mov mov mov mov ror xch xch xch xch xch xch xch rol add add add add add rorc addc addc addc addc addc rolc sub sub sub sub sub subc subc subc subc subc and and and and and or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp mov mov add addc sub subc and or xor cmp inc dec b, c sfr mov mov dbnz mov add addc sub subc and or xor cmp saddr mov dbnz inc dec !addr16 mov psw mov mov push pop [de] ror4 mov [hl] mov rol4 [hl + byte] [hl + b] [hl + c] mov x c mulu divuw
35 m pd78056fy, 78058fy (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw note only when rp = bc, de or hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr (4) call instruction/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand ax rp sfrp saddrp !addr16 sp #word addw subw cmpw movw movw movw movw ax movw note movw movw movw movw movw rp note xchw sfrp movw saddrp movw !addr16 movw sp movw none incw, decw push, pop second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 mov1 mov1 mov1 mov1 bt bf btclr bt bf btclr bt bf btclr bt bf btclr bt bf btclr set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 not1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction compound instruction br call br callf callt br, bc, bnc bz, bnz bt, bf btclr dbnz
36 m pd78056fy, 78058fy (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
37 m pd78056fy, 78058fy 11. electrical specifications absolute maximum ratings parameter symbol test conditions rating unit supply voltage v dd C0.3 to + 7.0 v av dd C0.3 to v dd + 0.3 v av ref0 C0.3 to v dd + 0.3 v av ref1 C0.3 to v dd + 0.3 v av ss C0.3 to + 0.3 v input voltage v i1 p00 to p07, p10 to p17,p20 to p27, p30 top37, p40 to p47, C0.3 to v dd + 0.3 v p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, x1, x2, xt2 reset v i2 p60 to p63 n-ch open-drain C0.3 to +16 v output voltage v o C0.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pin av ss C0.3 to av ref0 + 0.3 v high level output i oh 1 pin C10 ma current p01 to p06, p30-p37, p56, p57, p60 to p67, p120 to p127 total C15 ma p10 to p17, p20 to p27, p40 to p47, p50 to p55, C15 ma p70 to p72, p130, p131 total low level output i ol note 1 pin peak value 30 ma current effective value 15 ma p50 to p55 total peak value 100 ma effective value 70 ma p56, p57, p60 to p63 total peak value 100 ma effective value 70 ma p10 to p17, p20 to p27, p40 to p47, peak value 50 ma p70 to p72, p130, p131 total effective value 20 ma p01 to p06, p30 to p37, p64 to p67, peak value 50 ma p120 to p127 total effective value 20 ma operating ambient t a C40 to +85 c temperature storage t stg C65 to +150 c temperature note the effective value should be calculated as follows: [effective value] = [peak value] ? duty (t a = 25 c) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, alternate-function pin characteristics are the same as port pin characteristics.
38 m pd78056fy, 78058fy main system clock oscillation circuit characteristics (t a = C40 to 85 c, v dd = 2.7 to 6.0 v) recommended circuit typ. max. 5.0 4 5.0 10 30 5.0 500 unit mhz ms mhz ms mhz ns resonator ceramic resonator crystal resonator external clock parameter oscillator frequency (f x ) note 1 oscillation stabilization time note 2 oscillator frequency (f x ) note 1 oscillation stabilization time note 2 x1 input frequency (f x ) note 1 x1 input high/low level width (t xh , t xl ) notes 1. indicates only oscillation circuit characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wiring in the area enclosed with the broken line in the above figures should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v ss . ? do not ground wiring to a ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. 2. when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. min. 1.0 1.0 1.0 85 test conditions v dd = oscillator voltage range after v dd reaches oscil- lator voltage range min. v dd = 4.5 to 6.0 v x1 ic x2 c2 c1 x1 ic x2 c2 c1 x1 x2 m pd74hcu04
39 m pd78056fy, 78058fy subsystem clock oscillation circuit characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) min. 32 32 5 notes 1. indicates only oscillation circuit characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillator voltage min. resonator crystal resonator external clock parameter oscillator frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) test conditions typ. 32.768 1.2 max. 35 2 10 100 15 unit khz s khz m s cautions 1. when using the subsystem clock oscillator, wiring in the area enclosed with the broken line in the above figures should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v ss . ? do not ground wiring to a ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. 2. the subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. v dd = 4.5 to 6.0 v recommended circuit xt2 xt1 ic r1 c4 c3 xt1 xt2
40 m pd78056fy, 78058fy capacitance (t a = 25 c , v dd = v ss = 0 v) parameter symbol test conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance measured pins returned to 0 v. i/o c io f = 1 mhz p01 to p06, p10 to p17, 15 pf capacitance measured pins returned p20 to p27, p30 to p37, to 0 v. p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 p60 to p63 20 pf remark the characteristics of the alternate-function pins are the same as those of the port pins unless otherwise specified.
41 m pd78056fy, 78058fy parameter symbol test conditions min. typ. max. unit input voltage, v ih1 p10 to p17, p21, p23, p30 to p32, p35 to p37, p40 to p47, 0.7 v dd v dd v high p50 to p57, p64 to p67, p71, p120 to p127, p130, p131 v ih2 p00 to p06, p20, p22, p24 to p27, p33, p34, p70, p72, 0.8 v dd v dd v reset v ih3 p60 to p63 (n-ch open-drain) 0.7 v dd 15 v v ih4 x1, x2 v dd C0.5 v dd v v ih5 xt1/p07, xt2 v dd = 4.5 to 6.0 v 0.8 v dd v dd v 0.9 v dd v dd v input voltage, v il1 p10 to p17, p21, p23, p30 to p32, p35 to p37, p40 to p47, 0 0.3 v dd v low p50 to p57, p64 to p67, p71, p120 to p127, p130, p131 v il2 p00 to p06, p20, p22, p24 to p27, p33, p34, p70, p72, 0 0.2 v dd v reset v il3 p60 to p63 v dd = 4.5 to 6.0 v 0 0.3 v dd v 0 0.2 v dd v v il4 x1, x2 0 0.4 v v il5 xt1/p07, xt2 v dd = 4.5 to 6.0 v 0 0.2 v dd v 0 0.1 v dd v output voltage, v oh v dd = 4.5 to 6.0 v, i oh = C1ma v dd C1.0 v high i oh = C100 m av dd C0.5 v output voltage, v ol1 p50 to p57, p60 to p63 v dd = 4.5 to 6.0 v, 0.4 2.0 v low i ol = 15 ma p01 to p06, p10 to p17, p20 to p27, v dd = 4.5 to 6.0 v, 0.4 v p30 to p37, p40 to p47, p64 to p67, i ol = 1.6 ma p70 to p72, p120 to p127, p130, p131 v ol2 sb0, sb1, sck0 v dd = 4.5 to 6.0 v, 0.2 v dd v n-ch open-drain at pull-up time(r = 1 k w ) v ol3 i ol = 400 m a 0.5 v input leakage i lih1 v in = v dd p00 to p06, p10 to p17, p20 to 3 m a current, high p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p72, p120 to p127, p130, p131 reset i lih2 x1, x2, xt1/p07, xt2 20 m a i lih3 v in = 15 v p60 to p63 80 m a dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) remark the characteristics of alternate-function pins and a port pin are the same unless specified otherwise.
42 m pd78056fy, 78058fy parameter symbol test conditions min. typ. max. unit input leakage i lil1 v in = 0 v p00 to p06, p10 to p17, p20 to p27, C3 m a current, low p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, reset i lil2 x1, x2, xt1/p07, xt2 C20 m a i lil3 p60 to p63 C3 note m a output leakage i loh v out = v dd 3 m a current, high output leakage i lol v out = 0 v C3 m a current, low mask option r 1 v in = 0 v, p60 to p63 20 40 90 k w pull-up resistor software pull- r 2 v in = 0 v, p01 to p06, p10 to v dd = 4.5 v to 6.0 v 15 40 90 k w up resistor p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 20 500 k w to p67, p70 to p72, p120 to p127, p130, p131 dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) note when the pull-up resistor is not included in p60 to p63 (specified by a mask option), a C200 m a (max.) low- level input leakage current flows only at the 1.5 clock interval (no wait) when the read instruction to port 6 (pm6) and port mode register (pm6) is executed. at times other than this 1.5 interval, a C3 m a (max.) curent flows. remark the characteristics of alternate-function pins and port pins are the same unless specified otherwise.
43 m pd78056fy, 78058fy v dd = 5.0 v 10% note 5 412ma v dd = 3.0 v 10% note 6 0.6 1.8 ma v dd = 5.0 v 10% note 5 6.5 19.5 ma v dd = 3.0 v 10% note 6 0.8 2.4 ma v dd = 5.0 v 10% 1.4 4.2 ma v dd = 3.0 v 10% 0.5 1.5 ma v dd = 5.0 v 10% 1.6 4.8 ma v dd = 3.0 v 10% 0.65 1.95 ma v dd = 5.0 v 10% 60 120 m a v dd = 3.0 v 10% 32 64 m a v dd = 5.0 v 10% 25 55 m a v dd = 3.0 v 10% 5 15 m a v dd = 5.0 v 10% 1 30 m a v dd = 3.0 v 10% 0.5 10 m a v dd = 5.0 v 10% 0.1 30 m a v dd = 3.0 v 10% 0.05 10 m a dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol test conditions min. typ. max. unit notes 1. flows through the v dd and av dd pins. does not include the current which flows through the a/d converter, d/a converter, and on-chip pull-up resistor. 2. f xx = f x /2 operation (when oscillation mode selection register (osms) is set to 00h) 3. f xx = f x operation (when the osms is set to 01h) 4. when the main system clock is stopped 5. high-speed mode operation (when a processor clock control register (pcc) is set to 00h) 6. low-speed mode operation (when the pcc is set to 04h) remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillator frequency i dd1 5.0-mhz crystal oscillation operating mode (f xx = 2.5 mhz) note 2 power supply current note 1 5.0-mhz crystal oscillation operating mode (f xx = 5.0 mhz) note 3 i dd2 5.0-mhz crystal oscillation halt mode (f xx = 2.5 mhz) note 2 5.0-mhz crystal oscillation halt mode (f xx = 5.0 mhz) note 3 i dd3 32.768-khz crystal oscillation operating mode note 4 i dd4 32.768-khz crystal oscillation halt mode note 4 i dd5 xt1 = v dd stop mode when feedback resistor is used i dd6 xt1 = v dd stop mode when feedback resistor is not used
44 m pd78056fy, 78058fy parameter symbol test conditions min. typ. max. unit cycle time t cy operating on main 0.8 64 m s (min. instruction system clock v dd = 4.5 to 6.0 v 0.4 32 m s execution time) 0.8 32 m s operating on subsystem clock 40 122 125 m s ti00 input high-/ t tih00 , t til00 v dd = 4.5 to 6.0 v 2/f sam +0.1 note 3 m s low-level width 2/f sam +0.2 note 3 m s ti01 input high-/ t tih01 , t til01 10 m s low-level width ti1, ti2 input f ti1 v dd = 4.5 to 6.0 v 0 4 mhz frequency 0 275 khz ti1, ti2 input t tih1 , t til1 v dd = 4.5 to 6.0 v 100 ns high-/low-level 1.8 m s width interrupt request t inth , t intl intp0 v dd = 4.5 to 6.0 v 2/f sam +0.1 note 3 m s input high-/low 2/f sam +0.2 note 3 m s -level width intp1 to intp6, kr0 to kr7 10 m s reset t rsl 10 m s low-level width ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) f xx = f x /2 note 1 f xx = f x note 2 remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency notes 1. when oscillation mode selection register is set to 00h 2. when oscillation mode selection register is set to 01h 3. in combination with bits 0 (scs0) and 1 (scs1) of sampling clock select register (scs), selection of f sam is possible between f xx /2 n , f xx /32, f xx /64 and f xx /128 (when n= 0 to 4).
45 m pd78056fy, 78058fy t cy vs v dd (at f xx = f x main system clock operation) t cy vs v dd (at f xx = f x /2 main system clock operation) 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range cycle time t cy [ s] m 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range cycle time t cy [ s] m
46 m pd78056fy, 78058fy (2) read/write operation parameter symbol test conditions min. max. unit astb high-level width t asth 0.85t cy C 50 ns address setup time t ads 0.85t cy C 50 ns address hold time t adh 50 ns data input time from address t add1 (2.85+2n)t cy C80 ns t add2 (4+2n)t cy C100 ns data input time from rd t rdd1 (2+2n)t cy C100 ns t rdd2 (2.85+2n)t cy C100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (2+2n)t cy C60 ns t rdl2 (2.85+2n)t cy C60 ns wait input time from rd t rdwt1 0.85t cy C50 ns t rdwt2 2t cy C60 ns wait input time from wr t wrwt 2t cy C60 ns wait low-level width t wtl (1.15+2n)t cy (2+2n)t cy ns write data setup time t wds (2.85+2n)t cy C100 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.85+2n)t cy C60 ns rd delay time from astb t astrd 25 ns wr delay time from astb t astwr 0.85t cy + 20 ns astb - delay time from t rdast 0.85t cy C 10 1.15t cy + 20 ns rd - in external fetch address hold time from t rdadh 0.85t cy C 50 1.15t cy + 50 ns rd - in external fetch write data output time from rd - t rdwd 40 ns write data output time from wr t rdwd 050ns address hold time from wr - 0.85t cy 1.15t cy + 40 ns rd - delay time from wait - t wtrd 1.15t cy + 40 3.15t cy + 40 ns wr - delay time from wait - t wtwr 1.15t cy + 30 3.15t cy + 30 ns t wradh remarks 1. mcs: oscillation mode selection register (osms) bit 0 2. pcc2 to pcc0: processor clock control register (pcc) bit 2 to bit 0 3. t cy = t cy /4 4. n indicates the number of waits. (a) when mcs = 1, pcc2 to pcc0 = 000b (t a = C40 to + 85 c, v dd = 4.5 to 6.0 v)
47 m pd78056fy, 78058fy parameter symbol test conditions min. max. unit astb high-level width t asth t cy C 80 ns address setup time t ads t cy C 80 ns address hold time t adh 0.4t cy C 10 ns data input time from address t add1 (3+2n)t cy C160 ns t add2 (4+2n)t cy C200 ns data input time from rd t rdd1 (1.4+2n)t cy C70 ns t rdd2 (2.4+2n)t cy C70 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.4+2n)t cy C20 ns t rdl2 (2.4+2n)t cy C20 ns wait input time from rd t rdwt1 t cy C100 ns t rdwt2 2t cy C100 ns wait input time from wr t wrwt 2t cy C100 ns wait low-level width t wtl (1+2n)t cy (2+2n)t cy ns write data setup time t wds (2.4+2n)t cy C60 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.4+2n)t cy C20 ns rd delay time from astb t astrd 0.4t cy C30 ns wr delay time from astb t astwr 1.4t cy C30 ns astb - delay time from t rdast t cy C10 t cy + 20 ns rd - in external fetch address hold time from t rdadh t cy C 50 t cy + 50 ns rd - in external fetch write data output time from rd - t rdwd 0.4t cy C 20 ns write data output time from wr t wrwd 060ns address hold time from wr - t wradh t cy t cy + 60 ns rd - delay time from wait - t wtrd 0.6t cy + 180 2.6t cy + 180 ns wr - delay time from wait - t wtwr 0.6t cy + 120 2.6t cy + 120 ns (b) except when mcs = 1, pcc2 to pcc0 = 000b (t a = C40 to + 85 c, v dd = 2.7 to 6.0 v) remarks 1. mcs: oscillation mode selection register (osms) bit 0 2. pcc2 to pcc0: processor clock control register (pcc) bit 2 to bit 0 3. t cy = t cy /4 4. n indicates the number of waits.
48 m pd78056fy, 78058fy (3) serial interface (t a = C40 to +85 c, v dd = 2.7 to 6.0 v) ( a) serial interface channel 0 ( i) 3-wire serial i/o mode (sck0... internal clock output) parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 1600 ns t kh1 , t kl1 v dd = 4.5 to 6.0 v t kcy1 /2C50 ns t kcy1 /2C100 ns t sik1 v dd = 4.5 to 6.0 v 100 ns 150 ns t ksi1 400 ns 300 ns sck0 cycle time (ii) 3-wire serial i/o mode (sck0... external clock input) t kcy1 sck0 cycle time sck0 high-/low-level width c = 100 pf note t kso1 so0 output delay time from sck0 si0 setup time (to sck0 - ) note c is the load capacitance of the sck0 and so0 output lines. t kcy2 sck0 rise, fall time parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 1600 ns t kh2 , t kl2 v dd = 4.5 to 6.0 v 400 ns 800 ns t sik2 100 ns t ksi2 400 ns 300 ns t r2 , when using external device 160 ns t f2 expansion function when not using external 1000 ns device expansion function c = 100 pf note note c is the load capacitance of the so0 output line. sck0 high-/low-level width si0 setup time (to sck0 - ) so0 output delay time from sck0 t kso2 si0 hold time (to sck0 - ) si0 hold time (to sck0 - )
49 m pd78056fy, 78058fy parameter symbol test conditions min. typ. max. unit t kcy4 1600 ns t kh4 650 ns t kl4 800 ns t sik4 100 ns t ksi4 t kcy4 /2 ns t kso4 v dd = 4.5 to 6.0 v 0 300 ns 0 500 ns t r4 , when using external device 160 ns t f4 expansion function when not using external device 1000 ns expansion function parameter symbol test conditions min. typ. max. unit t kcy3 1600 ns t kh3 t kcy3 /2C160 ns t kl3 v dd = 4.5 to 6.0 v t kcy3 /2C50 ns t kcy3 /2C100 ns t sik3 v dd = 4.5 to 6.0 v 300 ns 350 ns t ksi3 600 ns t kso3 0 300 ns (iii) 2-wire serial i/o mode (sck0... internal clock output) sck0 cycle time sck0 high-level width sck0 low-level width sb0, sb1 setup time (to sck0 - ) sb0, sb1 hold time (to sck0 - ) sb0, sb1 output delay time from sck0 r = 1 k w , c = 100 pf note (iv) 2-wire serial i/o mode (sck0... external clock input) sck0 cycle time note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. sck0 high-level width sck0 low-level width sb0, sb1 setup time (to sck0 - ) sb0, sb1 hold time (to sck0 - ) sb0, sb1 output delay time from sck0 r = 1 k w , c = 100 pf note sck0 rise, fall time note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines.
50 m pd78056fy, 78058fy parameter symbol test conditions min. typ. max. unit scl cycle time t kcy5 r = 1 k w ,v dd = 2.7 to 6.0 v 10 m s c = 100 pf note 20 m s scl high-level width t kh5 v dd = 2.7 to 6.0 v t kcy5 160 ns t kcy5 190 ns scl low-level width t kl5 v dd = 4.5 to 6.0 v t kcy5 50 ns t kcy5 100 ns sda0, sda1 setup t sik5 v dd = 2.7 to 6.0 v 200 ns time (to scl - ) 300 ns sda0, sda1 t ksi5 0ns hold time (to scl ) sda0, sda1 output t kso5 v dd = 4.5 to 6.0 v 0 300 ns delay time from scl 0 500 ns scl - ? sda0, sda1 t ksb 200 ns scl - ? sda0, sda1 - sda0, sda1 ? scl t sbk 400 ns sda0, sda1 t sbh 500 ns high-level width note r and c are the load resistance and load capacitance of the scl, sda0, and sda1 output lines. (vi) i 2 c bus mode (scl... external clock input) parameter symbol test conditions min. typ. max. unit scl cycle time t kcy6 1000 ns scl high-/low-level t kh6 , 400 ns width t kl6 sda0, sda1 setup t sik6 200 ns time (to scl - ) sda0, sda1 hold t ksi6 0ns time (to scl ) sda0, sda1 output t kso6 r = 1 k w v dd = 4.5 to 6.0 v 0 300 ns delay time from scl c = 100 pf note 0 500 ns scl - ? sda0, sda1 t ksb 200 ns scl - ? sda0, sda1 - sda0, sda1 ? scl t sbk 400 ns sda0, sda1 high-level t sbh 500 ns width scl rise, fall time t r6 , when using external device 160 ns expansion function t f6 when not using external device 1000 ns expansion function note r and c are the load resistance and load capacitance of the sda0 and sda1 output lines. (v) i 2 c bus mode (scl... internal clock output) or or
51 m pd78056fy, 78058fy so1 output delay time from sck1 parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 1600 ns v dd = 4.5 to 6.0 v 400 ns 800 ns 100 ns 400 ns c = 100 pf note 300 ns t r8 , when using external device 160 ns t f8 expansion function when not using external 1000 ns device expansion function note c is the load capacitance of the sck1 and so1 output lines. sck1 cycle time parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 1600 ns v dd = 4.5 to 6.0 v t kcy7 /2C50 ns t kcy7 /2C100 ns v dd = 4.5 to 6.0 v 100 ns 150 ns 400 ns c = 100 pf note 300 ns (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1...internal clock output) t kcy7 t kh7 t kl7 t sik7 sck1 high-/low-level width si1 setup time (to sck1 - ) (ii) 3-wire serial i/o mode (sck1...external clock input) t kcy8 sck1 cycle time t ksi7 t kso7 note c is the load capacitance of the so1 output line. si1 hold time (to sck1 - ) t sik8 t ksi8 t kso8 sck1 high-/low-level width t kh8 t kl8 si1 setup time (to sck1 - ) si1 hold time (to sck1 - ) so1 output delay time from sck1 sck1 rise, fall time
52 m pd78056fy, 78058fy parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 1600 ns v dd = 4.5 to 6.0 v 400 ns 800 ns 100 ns 400 ns c = 100 pf note 300 ns when using external device 160 ns expansion function when not using external 1000 ns device expansion function parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 1600 ns v dd = 4.5 to 6.0 v t kcy9 /2C50 ns t kcy9 /2C100 ns v dd = 4.5 to 6.0 v 100 ns 150 ns 400 ns c = 100 pf note 300 ns t kcy9 /2C100 t kcy9 /2+100 ns t kcy9 C30 t kcy9 +30 ns 100 ns v dd = 4.5 to 6.0 v 100 ns 150 ns 2t kcy9 ns (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1... internal clock output) sck1 cycle time sck1 high-/low-level width si1 setup time (to sck1 - ) si1 hold time (to sck1 - ) so1 output delay time from sck1 t kcy9 t kh9 t kl9 t sik9 t ksi9 t kso9 stb - from sck1 - strobe signal high-level width busy signal setup time (to busy signal detection timing) busy signal hold time (to busy signal detection timing) sck1 from busy inactive t sbd t sbw t bys t byh t sps (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1... external clock input) note c is the load capacitance of the sck1 and so1 output lines. t kcy10 sck1 cycle time sck1 high-/low-level width note c is the load capacitance of the so1 output line. si1 hold time (from sck1 - ) si1 setup time (to sck1 - ) sck1 rise, fall time so1 output delay time from sck1 t kh10, t kl10 t sik10 t ksi10 t kso10 t r10 , t f10
53 m pd78056fy, 78058fy parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 1600 ns v dd = 4.5 to 6.0 v t kcy11 /2C50 ns t kcy11 /2C100 ns v dd = 4.5 to 6.0 v 100 ns 150 ns 400 ns c = 100 pf note 300 ns (c) serial interface channel 2 (i) 3-wire serial i/o mode (sck2...internal clock output) t kcy11 sck2 cycle time sck2 high-/low-level width si2 setup time (to sck2 - ) si2 hold time (to sck2 - ) so2 output delay time from sck2 t kh11, t kl11 t sik11 t ksi11 t kso11 note c is the load capacitance of the sck2 and so2 output lines. (ii) uart mode (dedicated baud rate generator output) parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 78125 bps 39063 bps transfer rate
54 m pd78056fy, 78058fy parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 1600 ns v dd = 4.5 to 6.0 v 400 ns 800 ns v dd = 4.5 to 6.0 v 39063 bps 19531 bps asck rise, fall time t r12 ,v dd = 4.5 to 6.0 v, 1000 ns t f12 when not using external device expansion function. 160 ns (iii) uart mode (external clock input) asck cycle time asck high-/low-level width transfer rate t kcy12 t kh12 , t kl12
55 m pd78056fy, 78058fy ac timing test point (excluding x1, xt1 input) clock timing ti timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points t til00 , t til01 t tih00 , t tih01 ti00, ti01 1/f ti t tih1 t til1 ti1, ti2 t xl t xh 1/f x v dd -0.5 v 0.4 v t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input
56 m pd78056fy, 78058fy read/write operation external fetch (no wait) : external fetch (wait insertion) : t asth t adh t add1 hi-z t ads t rdd1 t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd higher 8-bit address instruction code lower 8-bit address t asth t adh t add1 hi-z t ads t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd t wtrd t wtl t rdwt1 wait t rdd1 higher 8-bit address instruction code lower 8-bit address
57 m pd78056fy, 78058fy external data access (no wait) : external data access (wait insertion) : t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wrwd t astwr t wradh higher 8-bit address write data read data lower 8-bit address t rdd2 t wdh t rdwt2 t wtl t wrwt t wtwr t wtl wait t wtrd t rdwd t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wrwd t astwr t wradh higher 8-bit address write data read data lower 8-bit address t rdd2 t wdh t rdwd
58 m pd78056fy, 78058fy serial transfer timing 3-wire serial i/o mode : 2-wire serial i/o mode : t kso3,4 t sik3,4 t kcy3,4 t kl3,4 t kh3,4 sck0 t ksi3,4 sb0, sb1 t f4 t r4 i 2 c bus mode t f6 t r6 t kcy5, 6 t kl5, 6 t ksi5, 6 t kh5, 6 t kso5, 6 t sik5, 6 t ksb t sbk t ksb t sbh t sbk scl sda0, sda1 t kcym t klm t khm sck0 to sck2 si0 to si2 so0 to so2 t sikm t ksim t ksom input data output data t rn t fn m = 1, 2, 7, 8, 11 n = 2, 8
59 m pd78056fy, 78058fy 3-wire serial i/o mode with automatic transmit/receive function : 3-wire serial i/o mode with automatic transmit/receive function (busy processing) : note the signal is not actually driven low here; it is shown as such to indicate the timing. uart mode (external clock input) : t bys sck1 t sps busy (active high) 789 note 10 note 10+n note 1 t byh t sbw t sbd t kcy9,10 t kh9,10 t ksi9,10 t kso9,10 t sik9,10 d2 d1 d0 d7 d7 d2 d1 d0 so1 si1 sck1 stb t r10 t kl9,10 t f10 t kcy12 t kh12 t kl12 t f12 t r12 asck
60 m pd78056fy, 78058fy a/d converter characteristics (t a = C40 to +85 c, av dd = v dd = 2.7 to 6.0 v, av ss = v ss = 0 v) parameter symbol test conditions min. typ. max. unit 888bit 2.7 v av ref0 av dd 0.6 % t conv 19.1 200 m s t samp 12/f xx m s v ian av ss av ref0 v av ref0 2.7 av dd v r airef0 4 14 k w resolution overall error note conversion time sampling time analog input voltage reference voltage resistance between av ref0 and av ss resolution overall error settling time output resistance analog reference voltage resistance between av ref1 and av ss note overroll error excluding quantization error ( 1/2 lsb). it is indicated as a ratio to the full-scale value. caution for pins which also function as port pins, do not perform the following operations during a/d conversion. if these operations are performed, the total error ratings cannot be kept (except for lcd segment output alternate-function pin). (1) rewrite the output latch while the pin is used as a port pin. (2) change the output level of the pin used as an output pin, even if it is not used as a port pin. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency d/a converter characteristics (t a = C40 to +85 c, v dd = 2.7 to 6.0 v, av ss = v ss = 0 v) parameter symbol test conditions min. typ. max. unit 8 bit r = 2m w note 1 1.2 % r = 4m w note 1 0.8 % r = 10m w note 1 0.6 % note 1 4.5 v av ref1 6.0 v 10 m s c=30pf 2.7 v av ref1 < 4.5 v 15 m s r o note 2 10 k w av ref1 2.0 v dd v r airef1 dacs0, dacs1 = 55h note 2 48 k w notes 1. r and c are the load resistance and load capacitance of the d/a converter output pins. 2. value for d/a converter 1 channel remark dacs0, dacs1: d/a conversion value setting register 0, 1
61 m pd78056fy, 78058fy parameter symbol test conditions min. typ. max. unit data retention power v dddr 1.8 6.0 v supply voltage data retention i dddr v dddr = 1.8 v 0.1 10 m a power supply subsystem clock stop and feed-back resistor current disconnected release signal set time t srel 0 m s oscillation stabiliza- t wait release by reset 2 17 /fx ms tion wait time release by interrupt request note ms data memory stop mode low supply voltage data retention characteristics (t a = C40 to + 85 c) note in combination with bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register, selection of 2 12 /f xx and 2 14 /f xx to 2 17 /f xx is possible. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr
62 m pd78056fy, 78058fy interrupt request input timing reset input timing t intl t inth intp0 to intp6 t rsl reset
63 m pd78056fy, 78058fy 12. package drawings m pd78056fygc- -3b9, 78058fygc- -3b9 remark dimensions and materials of es product are the same as those of mass-production products. 80 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. l 0.8?.2 0.031 +0.009 ?.008 m 0.15 0.006 n 0.10 0.004 p 2.7 0.106 a 17.2?.4 0.677?.016 b 14.0?.2 0.551 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 d 17.2?.4 0.677?.016 f 0.825 0.032 g 0.825 0.032 h 0.30?.10 0.012 +0.004 ?.005 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) q 0.1?.1 0.004?.004 r5 ? 5 ? +0.10 ?.05 +0.004 ?.003 m m l k j h q p n r detail of lead end i g k 1.6?.2 0.063?.008 60 61 40 80 1 21 20 41 a b cd f s s80gc-65-3b9-4 s 3.0 max. 0.119 max.
64 m pd78056fy, 78058fy m pd78056fygc- -8bt, 78058fygc- -8bt 80 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. p80gc-65-8bt f 0.825 0.032 b 14.00?.20 0.551 +0.009 ?.008 s 1.70 max. 0.067 max. m 0.17 0.007 +0.001 ?.003 +0.03 ?.07 +0.009 ?.008 c 14.00?.20 0.551 +0.009 ?.008 a 17.20?.20 0.677?.008 g 0.825 0.032 h 0.32?.06 0.013 +0.002 ?.003 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) k 1.60?.20 0.063?.008 l 0.80?.20 0.031 +0.009 ?.008 n 0.10 0.004 p 1.40?.10 0.055?.004 q 0.125?.075 0.005?.003 r3 3 +7 ? +7 ? d 17.20?.20 0.677?.008 41 60 40 61 21 80 20 1 m s q r k m l a b c d j h i f g p n detail of lead end
65 m pd78056fy, 78058fy remark dimensions and materials of es product are the same as those of mass-production products. 80 pin plastic tqfp (fine pitch) (12 12) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 14.0?.2 0.551 +0.009 ?.008 b 12.0?.2 0.472 +0.009 ?.008 c 12.0?.2 0.472 +0.009 ?.008 d 14.0?.2 0.551 +0.009 ?.008 f g 1.25 1.25 0.049 0.049 h 0.22 0.009?.002 p80gk-50-be9-4 s 1.27 max. 0.050 max. k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 m 0.145 0.006?.002 n 0.10 0.004 p 1.05 0.041 q 0.05?.05 0.002?.002 r 55 55 +0.05 ?.04 +0.055 ?.045 b c d j h i g f p n l k m q r detail of lead end m 61 60 41 40 21 20 1 80
66 m pd78056fy, 78058fy 13. recommended soldering conditions this product should be soldered and mounted under the conditions recommended in the table below. for detail of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 13-1. surface mounting type soldering conditions (1/2) (1) m pd78056fygc- -3b9 : 80-pin plastic qfp (14 14 mm, resin thickness 2.7 mm) m pd78058fygc- -3b9 : 80-pin plastic qfp (14 14 mm, resin thickness 2.7 mm) ir35-00-3 package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), number of times: three times max. package peak temperature: 215 c, duration: 40 sec. max. (at 200 c or above), number of times: three times max. solder bath temperature : 260 c max., duration : 10 sec. max., number of times: once, preheating temperature : 120 c max. (package surface temperature) pin temperature: 300 c max. duration: 3 sec. max. (per pin row) soldering conditions soldering method infrared reflow recommended condition symbol vps wave soldering partial heating vp15-00-3 ws60-00-1 caution use of more than one soldering method should be avoided (except in the case of partial heating). ir35-00-2 package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), number of times: twice max. package peak temperature: 215 c, duration: 40 sec. max. (at 200 c or above), number of times: twice max. solder bath temperature : 260 c max., duration : 10 sec. max., number of times: once, preheating temperature : 120 c max. (package surface temperature) pin temperature: 300 c max. duration: 3 sec. max. (per pin row) soldering conditions soldering method infrared reflow recommended condition symbol vps wave soldering partial heating vp15-00-2 ws60-00-1 caution use of more than one soldering method should be avoided (except in the case of partial heating). (2) m pd78056fygc- -8bt : 80-pin plastic qfp (14 14 mm, resin thickness 1.4 mm) m pd78058fygc- -8bt : 80-pin plastic qfp (14 14 mm, resin thickness 1.4 mm)
67 m pd78056fy, 78058fy table 13-1. surface mounting type soldering conditions (2/2) (3) m pd78058fygk- -be9: 80-pin plastic qfp (fine pitch) (12 12 mm) infrared reflow vps package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), number of times: three times max., time limit: 7 days note (thereafter 10 hours 125 c prebaking required) package peak temperature: 215 c, duration: 40 sec. max. (at 200 c or above), number of times: three times max., time limit: 7 days note (thereafter 10 hours 125 c prebaking required) solder bath temperature: 260 c max., duration:10 sec. max., number of times: once, preheating temperature: 120 c max. (package surface tempeature). time limit: 7 days note (therefore 10 hours 125 c prebaking required) pin temperature: 300 c max. duration: 3 sec. max. (per pin row) soldering conditions soldering method recommended condition symbol ir35-107-3 wave soldering partial heating vp15-107-3 ws60-107-1 note for the storage period after dry-pack decompression storage conditions are max. 25 c, 65 % rh. caution use of more than one soldering method should be avoided (except in the case of partial heating).
68 m pd78056fy, 78058fy ie-78000-r in-circuit emulator common to 78k/0 series ie-78000-r-a 78k/0 series common to in-circuit emulator (for integrated debugger) ie-78000-r-bk break board common to 78k/0 series ie-78064-r-em note 8 emulation board common to m pd78064 subseries ie-780308-r-em emulation board common to m pd780308 subseries ie-78000-r-sv3 interface adapter and cable when ews is used as host machine (for ie-78000-r-a) ie-70000-98-if-b interface adapter when pc-9800 series (except notebook type) is used as host machine. ie-70000-98n-if interface adapter and cable when notebook type pc-9800 series is used as host machine. ie-70000-pc-if-b interface adapter when ibm pc/at tm and compatibles are used as host machine. ep-78230gc-r emulation probe common to m pd78234 subseries ep-78054gk-r emulation probe common to m pd78054 subseries ev-9200gc-80 socket to be mounted on the target system board manufactured for 80-pin plastic qfp (gc-3b9, gc-8bt type) tgk-080sdw adapter to be mounted in the target system board manufactured for 80-pin plastic tqfp (gk-be9 type) product made by tokyo eletech corporation ((03) 5295-1661). contact an nec dealer regarding the purchase of this product. sm78k0 notes 5, 6, 7 system simulator common to 78k/0 series id78k0 notes 4, 5, 6, 7 integrated debugger for ie-78000-r sd78k/0 notes 1, 2 ie-78000-r screen debugger df78054 notes 1, 2, 4, 5, 6, 7 m pd78054 subseries device file appendix a. development tools the following development tools are available for system development using the m pd78058fy subseries. language processing software ra78k/0 notes 1, 2, 3, 4 cc78k/0 notes 1, 2, 3, 4 df78054 notes 1, 2, 3, 4 cc78k/0-l notes 1, 2, 3, 4 prom writing tools pg-1500 pa-78p054gc pg-1500 controller notes 1, 2 assembler package common to 78k/0 series c compiler package common to 78k/0 series device file common to m pd78054 subseries c compiler library source file common to 78k/0 series prom programmer programmer adapters connected to pg-1500 pg-1500 control program debugging tools
69 m pd78056fy, 78058fy rx78k/0 notes 1, 2, 3, 4 real-time os for 78k/0 series mx78k0 notes 1, 2, 3, 4 real-time os for 78k/0 series real-time os fuzzy inference development support system fuzzy knowledge data creation tool translator fuzzy inference module fussy inference debugger fe9000 note 1 / fe9200 note 6 ft9080 note 1 / ft9085 note 2 fi78k0 notes 1, 2 fd78k0 notes 1, 2 notes 1. pc-9800 series (ms-dos tm ) based 2. ibm pc/at and compatibles (pc dos tm /ibm dos tm /ms-dos) based 3. hp9000 series 300 tm (hp-ux tm ) based 4. hp9000 series 700 tm (hp-ux) based, sparcstation tm (sunos tm ) based, ews4800 series (ews-ux/ v) based 5. pc-9800 series (ms-dos + windows tm ) based 6. ibm pc/at and compatibles (pc dos/ibm dos/ms-dos + windows) based 7. news tm (news-os tm ) based 8. maintenance product remarks 1. for third party development tools, see 78k/0 series selection guide (u11126e) . 2. the ra78k/0, cc78k/0, sm78k0, id78k0, sd78k/0, rx78k/0 are used in combination with the df78054.
70 m pd78056fy, 78058fy appendix b. related documents device related documents document name document no. document no. (english) (japanese) m pd78058f, 78058fy subseries users manual u12068e u12068j m pd78056fy, 78058fy data sheet this document u10121j m pd78p058fy data sheet u12076e u12076j 78k/0 series users manual-instruction u12326e u12326j 78k/0 series instruction set C u10904j 78k/0 series instruction table C u10903j caution the above related documents are subject to change without notice. be sure to read the latest documents before designing.
71 m pd78056fy, 78058fy development tool related documents (users manual) document name document no. document no. (english) (japanese) ra78k series assembler package operation eeu-1399 eeu-809 language eeu-1404 eeu-815 ra78k series structured assembler preprocessor eeu-1402 u12323j ra78k0 assembler package operation u11802e u11802j assembly language u11801e u11801j structured assembly language u11789e u11789j cc78k series c compiler operation eeu-1280 eeu-656 language eeu-1284 eeu-655 cc78k0 c compiler operation u11517e u11517j language u11518e u11518j cc78k/0 c compiler application note programming know-how eea-1208 eea-618 cc78k series library source file C u12322j pg-1500 prom programmer eeu-1335 u11940j pg-1500 controller pc-9800 series (ms-dos) based eeu-1291 eeu-704 pg-1500 controller ibm pc series (pc dos) based u10540e eeu-5008 ie-78000-r u11376e u11376j ie-78000-r-a u10057e u10057j ie-78000-r-bk eeu-1427 eeu-867 ie-78064-r-em eeu-1443 eeu-905 ie-780308-r-em u11362e u11362j ep-78230 eeu-1515 eeu-985 ep-78054gk-r eeu-1468 eeu-932 sm78k0 system simulator, windows based reference u10181e u10181j sm78k series system simulator external parts user open u10092e u10092j interface specification id78k0 integrated debugger, ews based reference C u11151j id78k0 integrated debugger, pc based reference u11539e u11539j id78k0 integrated debugger, windows based guide u11649e u11649j sd78k/0 screen debugger introduction C eeu-852 pc-9800 series (ms-dos) based reference C u10952j sd78k/0 screen debugger introduction u10539e eeu-5024 ibm pc/at (pc dos) based reference u11279e u11279j caution the above related documents are subject to change without notice. be sure to read the latest documents before designing.
72 m pd78056fy, 78058fy document name document no. document no. (english) (japanese) 78k/0 series real-time os fundamental u11537e u11537j installation u11536e u11536j 78k/0 series os mx78k0 fundamental u12257e u12257j fuzzy knowledge data creation tool eeu-1438 eeu-829 78k/0, 78k/ii, 87ad series eeu-1444 eeu-862 fuzzy inference development support system translator 78k/0 series fuzzy inference development support system eeu-1441 eeu-858 fuzzy inference module 78k/0 series fuzzy inference development support system eeu-1458 eeu-921 fuzzy inference debugger embedded software documents (users manual) document name document no. document no. (english) (japanese) ic package manual c10943x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor devices c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j electrostatic discharge (esd) test C mem-539 guide to quality assurance for semiconductor devices mei-1202 c11893j microcomputer product series guide C u11416j other documents caution the above related documents are subject to change without notice. be sure to read the latest documents before designing.
73 m pd78056fy, 78058fy [memo]
74 m pd78056fy, 78058fy notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
75 m pd78056fy, 78058fy nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
m pd78056fy, 78058fy the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. fip is a trademark of nec corporation. iebus is a trademark of nec corporation. ms-dos and windows are either registered trademarks of microsoft corporation in the united states and/or other countries. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. hp9000 series 300, hp9000 series, and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and nes-os are trademarks of sony corporation. purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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